The path towards building faster computing systems relies on increasingly smaller transistors to meet the growing demand for more computational power. Beyond modifying materials and geometries, some researchers are looking to carbon nanotubes as the next step beyond silicon’s miniaturisation barrier.
Current silicon-based chips use complementary metal oxide semiconductor (CMOS) technology. Intel predicts that scaling down silicon-based CMOS will be unsustainable for the industry at seven nanometres sometime after 2020. Near the start of 2018 Intel plans to launch its first 10-nanometre product – providing it does not delay its launch as it did in 2015. This is a sign that predictably doubling transistor density in conventional chips is becoming increasingly difficult. In the west, Intel, IBM and others are investing billions in novel chip R&D technologies, achieving small, iterative progress.
This structure of carbon in a hexagonal lattice shape can be thought of as a sheet of graphene rolled into a cylinder. The simplistic structure and key properties of graphene could herald a new age of transistor development – below seven nanometres. With conventional silicon transistors struggling to keep up, carbon nanotube-based transistors could provide a significant increase in computational performance.
Breaking the 10nm barrier
In the East, the reality of fabricating transistor prototypes that are smaller, more energy-efficient and less prone to overheat and fail just went up a gear. In January 2017, Chinese researchers from Peking University published in the journal Science their breakthrough in developing a carbon nanotube field-effect transistor (CNT FET) of just five nanometres in size; the first time this technology has reliably been scaled down under 10 nanometres, according to the research paper.
This, and similar innovations, will help the jump to better computing for big data projects, cybersecurity, atomic clocks and communication networks, to name a few areas.
This transistor is faster and operates at a much lower supply voltage – 0.4 volts instead of 0.7 volts – compared with a silicon-based CMOS transistor of the same scale.
‘Previously, IBM fabricated a nine nanometre p-type [channel category for electron current flow] field-effect transistor (FET), and a 20 nanometre CNT CMOS,’ said Lian-Mao Peng, the principal investigator of the study. ‘Our work pushed CNT CMOS transistors down to 10 nanometres, and a p-type FET down to five nanometers, which is likely the ultimate transistor size that the industry is likely to achieve.’
Peng’s team benchmarked their CNT FET with a sub-10 nanometre silicon transistor of similar dimensions using the ‘energy delay product’ (EDP). This metric is the average energy consumed per switching event and measures the overall performance by compromising between power dissipation and performance.
‘Our experimental data indicated that CNT FETs can improve EDP by a factor of 10, than that of silicon CMOS FETs at the sub-10 nanometre technology node. Future computers based on CNT integrated chips should run much faster (10 times) than the silicon based integrated chips with similar power dissipation — or will require 1/10 power dissipation of silicon circuits with similar performance,’ said Peng.
This demonstration is not only good news for future fabrication scalability of transistors, based on carbon nanotubes, but has the potential for better mobile communication devices according to Pertti Hakonen, professor of physics at Aalto University in Espoo, Finland — who was not involved in the study.
‘The concept introduced in the paper is quite interesting,’ said Hakonen. ‘The carbon nanotube is operated via graphene contacts, which act as the drain, and source electrodes that are reservoirs for charge carriers. Graphene contacts are modified by the gate electrode, but this is an integral part of the device. Consequently, the packing of devices can be made in a compact fashion. I believe this concept will be useful for many research groups working on miniaturisation of their circuits,’ said Hakonen.
Although the results presented by the Peking University researchers still needs to be reproduced in an industrial lab, researchers in the academic community commend the promising approach. ‘As far as I can judge, I do not see faults in their results,’ said Mikko Möttönen, leader of quantum computing and the devices lab at Aalto University, Finland, and professor in quantum computing at the University of Jyväskylä — who was also not involved in the study.
‘This is obviously a very important work for the future industrial transistor development. Issues with low-cost, high-yield mass production and ageing should be addressed.’
Credit: James A Isbell/Shutterstock
This achievement supports one of the main goals of the wider semiconductor industry’s partnership programme known as the International Technology Roadmap for Semiconductors (ITRS). One of the roadmap’s seven building blocks is to support ‘Beyond CMOS’ technologies. These are devices, focused on new physical states, which provide functional scaling.
‘Traditionally the problem in carbon has been that it is difficult to make good transparent contacts to typical metal,’ said Möttönen. This is because electrons travelling within carbon nanotubes are considered to be in very different physical states compared to their CMOS transistor counterparts.
Peng’s team, in their experiments, were able to use only one electron per switching operation in their five-nanometre scale CNT FET. The switching time of their CNT FET was about 42 femtoseconds. A femtosecond is one millionth of one billionth of a second; put another way, in Chemistry the time it takes for atoms in a molecule to perform one vibration is about 10-100 femtoseconds.
In comparison the switching time in a state-of-the-art silicon 14 nanometre transistor is 220 femtoseconds – the faster and lower power advantage of the CNT FET is due to the carbon nanotubes properties such as higher carrier mobility and a thinner body.
‘Some of these problems have now been solved and the remaining [issues] may be solved in the future. One of the other things is how to grow the CNTs exactly where one wants them to be,’ said Möttönen.
Because carbon nanotubes are grown like crystals, there is a certain randomness in how the final filament products end up. Even with the best automated design algorithms, impurities still end up in the material that results in electrical resistance, consuming more energy and reducing computation speeds. Some progress has been made in more efficient connections between carbon nanotubes and metal bonds by fusing the contacts directly.
‘One still needs to show that all parts of the transistor can be scaled down to the required size and that it can be done with very high yield. Also one needs to test that the transistors are very stable in time, i.e., none of them should break with years of operation time,’ said Möttönen.
Unperturbed by these hurdles, Peng is not shy in his ambitions for the semiconductor industry, as investors welcome the team’s breakthrough research.
‘According to our work, as well as those by IBM, there is a good chance that CNT FETs would extend Moore’s Law beyond 2020. Our long-time goal for the development of CNT transistors and integrated circuits is to promote CNT chip technology to become the mainstream chip technology, and to provide more powerful chips with higher speed and lower power dissipation for China and the world,’ said Peng.
Building a carbon nanotube bridge to quantum computers
Moreover, carbon nanotube-based transistors may open up the gateway to superconducting quantum-bits (qubits), which are perceived as a promising path for a scalable quantum system. Superconducting qubits are circuits made from superconducting components that offer zero-resistance to electrical currents at temperatures near absolute zero. The components can comprise materials such as yttrium barium copper oxide to create wires, capacitors or non-linear inductors.
Hakonen’s research goals are investigating the possibilities of combining graphene and carbon nanotubes for quantum technology, such as in simple-charge-based qubits. These architectures have excellent electrical properties to handle decoherence issues that greatly hinder performance and information reliability of qubits.
Credit: Robert Voight/Shutterstock.com
‘The advantage is that electrical charge fluctuations in clean nanotubes are very small compared with silicon devices, and long enough coherence times may be achievable in nanotube systems,’ said Hakonen. This is important for information stability on qubits as error rates are far more prominent and impactful than in a classical CMOS transistor.
Proof-of-concept devices have already been created that have reliable contacts between the metallic lead and tube. This is due to the combination of CNTs with special superconducting alloys made of molybdenum and rhenium. However, measurements on CNT qubit devices have concentrated on noise properties so far.
The next step is to see how long decoherence times can be reached in these novel qubits. Hakonen suspects that using superconducting nanowires instead could be a better approach, with lower component variation and easier to scale up.
For example, a technique known as molecular beam epitaxy enables the growth of thin films and wires of single crystals, or layers of semiconductors or other metals. These superconducting nanowires have already been grown and tested. Qubits with semiconductor nanowire Josephson junctions (two layers of superconductors separated by a thin insulating layer), known as a hybrid Gatemon two-qubit system, was demonstrated last year in the journal Physical Review Letters.
Both scientists Hakonen and Möttönen, whose expertise resides in quantum information systems, know not to put all their qubit eggs in one basket when it comes to CNT technology.
Certain computational problems will always elude carbon nanotube-based computers. Only future large-scale quantum computers will be able to find ways to solve problems, such as computing the energy transport in novel drug molecules in a reasonable amount of time, instead of the thousands or millions of years it would take on today’s best supercomputers.
For now, CNT technology investment is still risky, as there is no guarantee of payback. For example, Microsoft Research is focussing on designing ‘topological’ material qubits alongside their prototype software simulation environments.
‘Topological materials could provide yet another approach for quantum computation and this would be topologically protected; that is, basically decoherence-free,’ said Hakonen.
Currently efforts are being made to bridge graphene with silicon. The European Graphene Flagship project is researching the integration with silicon circuits. Their present objective is to produce components for optical communications using optical graphene detectors directly integrated with CMOS circuits.
However, current CMOS technology still has life in it yet. The semiconductor industry is investing in techniques it knows probably will produce healthy returns from production. In late 2016, the large semiconductor manufacturer GlobalFoundries, based in California, announced their roll-out plan to deliver a new seven nanometre FinFET semiconductor technology, with trials running this year. FinFET stand for Fin Field Effect transistor or a ‘3D’ transistor.
Intel just announced a $7 billion investment in a next-generation semiconductor factory to target the seven nanometre manufacturing process in Arizona, which they advertise to be the most advanced semiconductor factory in the world. The plan is for the plant to hire 3,000 high-tech engineering jobs and 10,000 long-term jobs to produce microprocessors to power data centres and hundreds of millions of smart and connected devices.
Although Peng still believes that CNT electronics will have a good chance to replace silicon CMOS technology at five nanometre nodes by 2022.
‘We are hoping to have more partners working together to create a healthy industry environment for CNT chip fabrication, through co-operating with industries and government,’ said Peng.
Whether or not carbon nanotubes will replace silicon by 2022, all of these ongoing developments compliment advancement into next generation transistors. It appears likely that more advanced nanowires, or a hybrid-integration approach or even precise 3D printing of composite materials, will push CMOS transistor performance further. This is unless, of course, another novel breakthrough transports us to faster, more reliable and easily mass-produced quantum computing. l
Adrian Giordani is a freelance science writer who previously worked for CERN. Adrian specialises in science communications particularly in the fields of open science, computing, future technologies and HPC.
