Automatically generating HDL code from Matlab, HDL Coder enables engineers to implement FPGA and ASIC designs from the Matlab language. MathWorks has also released HDL Verifier, which includes FPGA hardware-in-the-loop capabilities for testing FPGA and ASIC designs. With these two products, the company now provides HDL code generation and verification across Matlab and Simulink.
HDL Coder generates portable, synthesisable VHDL and Verilog code from Matlab functions and Simulink models that can be used for FPGA programming or ASIC prototyping and design. As a result, engineering teams can immediately identify the best algorithm for hardware implementation. Traceability between Simulink models and generated HDL code also supports the development of high-integrity applications that adhere to DO-254 and other standards.
HDL Verifier now supports FPGA hardware-in-the-loop verification for Altera and Xilinx FPGA boards. Additionally, it provides co-simulation interfaces that link Matlab and Simulink with Cadence Incisive, Mentor Graphics ModelSim, and Questa HDL simulators. With these capabilities, engineers can rapidly verify that their HDL implementation matches their Matlab algorithms and Simulink system specifications.
